Building An Ideal MOSFET

Electrical and computer engineering researchers demystify the role of negative capacitance in modern MOSFETs
Tuesday, May 26, 2020 - 09:45
Santa Barbara, CA

Kaustav Banerjee.jpg

Kaustav Banerjee

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As our electronics continue to proliferate and become more sophisticated, the race continues for more power efficient and scaleable semiconductor devices — components that use minimal power while being small enough to pack into increasingly dense integrated circuits.

MOSFETs (metal-oxide field-effect transistors) are an example of such a breakthrough. Developed in the 1960s, their low power consumption, scalability, compactness and ease of mass manufacture made them the go-to logic switch for a wide array of electronics. The rapid miniaturization and densification of these transistors (without a concurrent increase in power consumption) was what led Intel executive Gordon Moore to formulate his famous law: that the number of transistors in an integrated circuit would double every two years. The result has been a steady increase in the performance of our computers for several decades, from desktops and laptops to our smart devices and wearables. Today’s smartphones have billions of nanoscale MOSFETs.

However, the benefits of downward scaleability — at least in terms of conventional FETs — seems to be hitting a limit, according to UC Santa Barbara electrical and computer engineering professor Kaustav Banerjee, a renowned expert in nanoelectronics and one of the world’s most influential scientific minds, according to Clarivate Analytics. And though a certain type of transistor called a negative-capacitance FET (NC-FET) has been touted as a way to maintain performance, Banerjee thinks it’s time to reconsider its role.

“After over a decade of misconception and confusion in the scientific community, we have essentially blasted the myth that NC-FET is a steep-slope device,” Banerjee said of his paper, “Is negative capacitance FET a steep-slope logic switch?,” recently published in Nature Communications.

Voltage Saver

According to Banerjee, while smaller and less power consuming MOSFETs have indeed allowed for increased performance of our devices without a corresponding increase in the energy consumed, the power saving benefits of even smaller and lower voltage FETs seems to be coming to a close.

“Lowering the supply voltage has failed to keep pace with the feature-size scaling because the thermionic emission-based transport mechanism of MOSFETs and short-channel effects limit the steepness of their transfer characteristics,” Banerjee wrote.

Scientists and engineers have long been aware of these limits to current MOSFET technology and have been working to overcome these limitations by developing new transistors with “steep slopes.”

“Steepness” refers to the relationship between the current flowing through a device and its corresponding voltage; the steeper the slope, the more abrupt the change in current from OFF position to ON in an electronic switch. It’s a desirable quality for energy efficiency and performance, and a characteristic that electronics designers have tried to imbue into MOSFETs. ‘Steep-slope’ devices are defined in terms of a ‘subthreshold swing’ (SS) of less than 60 mV/dec. at room temperature.

Among the potential candidates for future steep-slope transistors have been the band-to-band tunnel FET (TFET), said Banerjee, whose group has demonstrated an atomically-flat TFET using 2D material in 2015, and the NC-FET, which uses the electronic properties of ferroelectric materials to stimulate negative capacitance in an effort to create the steep-slope effect. At a certain voltage, ferroelectric materials reverse polarization, creating an artificially engineered (through capacitance matching) stable (non-transient) state in which a decrease in voltage leads to an increase in charge. The charge stored on the material is used to amplify the supply voltage, allowing engineers to design electronics with a lower supply voltage requirement.  

However, Banerjee argues, while many types of NC-FETs have been created in various dimensions with different ferroelectric materials, performance-degrading phenomena continue to persist, including hysteresis and the absence of an average steep subthreshold slope over several orders of magnitude of current.

“Subthreshold voltage loss in modern (nanoscale) FETs always shows up,” he explained. “It is normally induced by parasitic capacitances such as from short-channel effect or interface traps. Those parasitic charges in channel lead to voltage loss across the gate oxide. However, in NCFETs, they also induce the polarization of NC layer, leading to the formation of negative voltage across the NC, which compensates for the voltage loss across the gate oxide.” Well-designed MOSFETs, according to the study, receive limited benefit from negative capacitance. In addition, the addition of what would be a “very thick” NC layer would be “impractical for state-of-the-art very-large-scale integration technology,” in an era of ultrathin-body design, said Banerjee.

A more practical role for negative capacitance in FETs, Banerjee said, would be as a voltage loss saver, by using its behavior to absorb overdrive voltage loss — excess voltage beyond the threshold voltage, which controls the transistor operation speed — thus also lowering energy wasted.

“Saving the subthreshold voltage loss allows the threshold voltage to approach the minimum threshold voltage of an ideal MOSFET, thereby enabling the scaling of supply voltage at fixed device performance,” he said.

According to Wei Cao, the first author of the paper, and a member of Banerjee’s Nanoelectronics Research Lab, “the main motivation behind this work is to point out that NC-FET is not a steep-slope switch; instead, it can help improve the performance of MOSFETs by means of saving the voltage loss caused by various short-channel effects in ultra-scaled devices and/or surface charge screening. Thereby, our work is expected to steer the research direction of the electron device community toward the right direction.”

Joe Qiu, the program manager at the Army Research Office (ARO) that partly supported this work said, "This research will have significant impact for enabling future generations of low-power MOSFETs and man-portable electronics which are of critical importance for the U.S. Army.” ARO is an element of the U.S. Army Combat Capabilities Development Command’s Army Research Laboratory.

Contact Info: 

Sonia Fernandez

(805) 893-4765

sonia(dot)fernandez(at)ucsb(dot)edu

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